The HiPChips Conference

Introduction

The wide deployment of Machine learning (ML) and high performance computing (HPC) applications has been driving the ever increasing computing demands in both data center and edge. With the slowing down of Moore’s law, heterogeneous computing with domain-specific accelerators (DSA) is deemed as a new computing paradigm to meet the performance requirements.

Heterogeneous computing with DSAs brings many opportunities as well as challenges when scaling up and scaling out the computation power. At the chip level, with the advancement of packaging technologies, the heterogeneous chiplet architecture is powerful to solve the complexity of traditional monolithic design and the increasing cost of silicon process. At the system level, composable architectures with resource disaggregation lead to dramatic improvement of the low resource utilization which often occurs due to the growing computation horsepower within a single computing device and fixed configurations of various system resources.

However, how to interconnect computing resources and orchestrate heterogeneous computing with efficient data movement at different scales is the key to success. Another big challenge industry currently faces is lack of standards for heterogeneous resources to work seamlessly across various software ecosystems.

The 2nd International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2023) specifically targets the novel researches and industry standards on advanced interconnect technologies, and how they impact on the designs of chiplet-based architectures as well as software ecosystems. The major objective of this workshop is to share the ideas of technology innovations and the latest development on but not limited to the following topics:

Optical and other advanced chiplet interconnect technologies

Interconnect standards of coherent and non-coherent data sharing protocols (e.g. CXL)

Disaggregated computing architectures powered by high speed interconnect

Chiplet architectures for in-memory computing and other emerging technologies

Software optimization and scheduling with fast inter-chiplet network

Power evaluation and performance modeling of chiplet architectures

For any submission information, please send your requests to organizers at hipchips2023@gmail.com

Organizers

Weifeng Zhang, Lightelligence
Dr. Weifeng Zhang is the Chief Architect and VP of Software at Lightelligence Inc, responsible for hardware software co-design and software ecosystem to empower optical computing and interconnect technologies. Prior to joining Lightelligence, Weifeng was a fellow of Alibaba Cloud and the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure. He was a founding member of the Board of Directors at MLCommons™ (MLPerf™) and currently serves as the Tech Chair of AI Co-Design Workgroup at Open Computing Project Foundation (OCP). Weifeng received his PhD in Computer Science from University of California, San Diego (UCSD).

Dharmesh Jani, Meta Platforms
Dharmesh Jani (‘DJ’) leads Infrastructure Technology Ecosystem and Partnerships at Meta and has been an active member of OCP since 2012. He is also co-chair of the OCP Incubation Committee where he started the OCP strategic initiatives, launched multiple projects such Sustainability and is a founding member of the Board of Directors for UCIe consortium. Prior to Meta, he has worked in Fortune 500 companies leading product development as well as in startups building zero to one businesses. He has BTech from IIT-Bombay, MSEE from UCLA and MBA from UC-Berkeley (Haas).

Vijay Janapa Reddi, Harvard University
Prof. Janapa Reddi is an Associate Professor in John A. Paulson School of Engineering and Applied Sciences at Harvard University, a founding member of MLCommons and serves on the MLCommons™ Board of Directors, and a Co-Chair of MLPerf Inference that is responsible for fair and useful benchmarks for measuring training and inference performance of ML hardware, software, and services.  Dr. Janapa Reddi is a recipient of multiple honors and awards, including the National Academy of Engineering (NAE) Gilbreth Lecturer Honor (2016), IEEE TCCA Young Computer Architect Award (2016), Intel Early Career Award (2013), Google Faculty Research Awards (2012, 2013, 2015, 2017, 2020), Best Paper at the 2005 International Symposium on Microarchitecture (MICRO), Best Paper at the 2009 International Symposium on High Performance Computer Architecture (HPCA), MICRO and HPCA Hall of Fame (2018 and 2019, respectively), and IEEE’s Top Picks in Computer Architecture awards (2006, 2010, 2011, 2016, 2017).  He received a Ph.D. in computer science from Harvard University.

Speakers

	Dr. Huaiyu Meng Co-Founder & CTO, Lightelligence PhD in Electrical Engineering from MIT, focusing on integrated photonics in CMOS platform for telecom, datacom, and bio-sensing applications. At Lightelligence, Huaiyu is responsible for product definition and technology roadmap planning.
	Dr. Kaisheng Ma Professor, Tsinghua University Principal Investigator of ARChip Lab at Tsinghua University. His research focuses on computer architecture, implanted devices, AI Algorithms Design, focusing on interpretation, robustness and compact model design.
	Dr. John Wuu Sr Fellow, AMD Leading AMD memory architecture, foundry memory technology interface, advanced memory technique development, and emerging memory technology evaluation and design. Deliver high performance caches, large arrays, and memory test chips.
	Nathan Kalyanasundharam Corporate Fellow, AMD Lead architect of AMD’s Infinity Fabric, responsible for delivering coherent interconnect protocol and technology across all AMD products. He is passionate about open standards to enable heterogenous computing. He is a member of the Board of Directors at Compute Express Link (CXL) and Universal Chiplet Interconnect Express(UCIE) consortia.
	Jeff Defilippi Sr Director Product Management, ARM Help ARM define architectures and IP products to address the computing needs of future cloud to edge infrastructure.
	Dr. Debendra Das Sharma UCIe Chair, Sr Fellow, Intel Chief Architect of I/O Technologies and Standards: Responsible for driving Intel-wide critical interconnect technologies in PCIe, CXL, Intel’s coherency interconnect, on-package interconnects, as well as on-die standards (PIPE, LPIF, CPI, SFI).
	Dr. Sajjad Moazeni Professor, University of Washington Ph.D. in Electrical Engineering and Computer Sciences from UC Berkeley. Interested in integrated system design and photonics with applications in computing and communication, sensing and imaging, and life sciences.
	Dr. Vijay Janapa Reddi Professor, Harvard University Direct the Edge Computing Lab at Harvard. Research interests span the definition of computer architecture, including software design and optimization, to enhance mobile quality-of-experience and improve the energy-efficiency of high-performance computing systems.
	Dr. Cliff Grossner VP of Marketing Intelligence & Innovation, OCP Driving awareness of Open Compute Projet Foundation (OCP) and guiding OCP futures technology initiative research directions.

Schedule

Sunday Feb 26th, 2023, 1:20pm - 5:40pm (EST)
Hotel Bonaventure, St Laurent #3
Zoom Meeting: over (YouTube video coming soon)

Session	Speaker	Title	Material
Open Remark 1:20-1:35pm	Dharmesh Jani Co-Chair	Chiplets for AI/ML: challenges and opportunities	slides
Invited talk 1:35-2:00pm	Dr. Huaiyu Meng Co-Founder & CTO	Optical Network-on-Chip for large scale chiplet architectures	slides
Invited talk 2:00-2:25pm	Dr. Kaisheng Ma Professor	A Scalable Methodology for Designing Efficient Interconnection Network of Chiplets	slides
Invited talk 2:25-2:50pm	Nathan K. Corporate Fellow John Wuu Sr Fellow	Challenges and Obstacles to Overcome to Reach Chiplet Nirvana	slides
Invited talk 2:50-3:15pm	Jeff Defilippi Sr Director	Building Heterogeneous Chiplets with AMBA Interconnects	slides
Coffee Break 3:15-3:30pm
Invited talk 3:30-3:55pm	Dr. Debendra Das Sharma UCIe Chair	Universal Chiplet Interconnect Express (UCIe)TM : An open standard for innovations at the package level	slides
Invited Talk 3:55-4:20pm	Dr. Sajjad Moazeni Professor	Next Generation Co-Packaged Optics for Future Disaggregated AI System	slides
Invited talk 4:20-4:45pm	Dr. Cliff Grossner VP of OCP	Establishing a New Open Chiplet Economy	slides
Close Remark 4:45-5:10pm	Dr. Weifeng Zhang Co-Chair	Enabling Polymorphic AI Architecture via Composable Chiplet Technologies	slides
Open Chat 5:10-6:00pm	Host: Prof. Vijay Janapa Reddi	Informal, open discussions for all attendees

Venue

HiPChips Conference is colocated with  HPCA 2023
The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA-29)
Montreal, Quebec, Canada