The HiPChips Conference

Introduction

The 1st International Workshop on High Performance Chiplet and Interconnect Architectures (HiPChips), sponsored by the Open Domain Specific Architecture (ODSA) Sub-Project, was held on June 19th, 2022, in conjunction with the 49th International Symposium on Computer Architecture (ISCA) in New York City, New York, USA (Attendee information).

The major objective of this workshop was to bring researchers from academia and industry together to communicate their ideas, share knowledge of advanced technologies and new development on but not limited to the following topics:

Chiplet-based accelerator level parallelism (ALP)

Chiplet architecture for large scale system design

Physical and logical inter-die interface design for heterogeneous architectures

Coherent and non-coherent data sharing protocols via fast chiplet interconnection

Chiplet architectures for in-memory computing and other emerging technologies

ODSA-based 3D architecture for efficient ML acceleration

Chiplet-based secure computing

Power evaluation and performance modeling of chiplet architecture

Software optimization framework with fast inter-chiplet network

Chiplet topology aware ML optimizations

Scheduling for massive heterogeneous chiplet-based processors

Machine learning (ML), high performance computing (HPC), and the convergence of both are becoming the major driving force to define future computer architectures in both data center and edge. As performance requirements of workloads have catapulted, heterogeneous computing with domain-specific accelerators (DSA) is deemed as a new computing paradigm to meet the computation demand in the post-Moore era.

While an accelerator architecture is still evolving to continuously integrate more components to boost its computing horsepower, the increasing cost of silicon results in the rise of chiplet architectures.

As a promising alternative to advance a chip design, chiplets take advantages of the recent development of packaging technologies to reduce the complexity of traditional monolithic system-on-a-chip (SoC) design by improving system-level interconnection density and reducing power consumption via mix-and-matching existing or new components and integrating them into a single package. The modularized approach presumably can shorten the development time and improve yield to lower the manufacturing costs. However, one of the biggest challenges industry currently faces is lack of standards and tools to allow different pieces of silicon across vendors to be tied together and work seamlessly through a common interface.

At the same time, as individual devices continue to shrink and more heterogeneous chiplets are integrated, innovations on chiplet-based computing architectures will be required. Though communication between chiplets is typically slower than on-chip communication, distances are shorter and there might be more conduits for inter -chip signals. Thus, collectively inter-chiplet communication may be faster with less energy consumption. So how to distribute data among chiplets and optimize data movement for efficient spatial parallel processing is another key to success.

The Open Compute Project Foundation (OCP) is a global industrial consortium with the mission to enable mainstream delivery of open and efficient designs for scalable computing. Its Open Domain-Specific Architecture (ODSA) working group was incubated to define the standards for a coherent cross-industry open ecosystem of chiplets and make a viable chiplet market a reality. ODSA is situated strategically to address challenges of chiplet interoperability due to inherent limitations of proprietary designs, including physical interfaces, chiplet base functionalities for top software stack, as well as packaging and testing of products across vendors.

ODSA's goal is to create an open chiplet marketplace that allows systems in packages to be built from building blocks from multiple vendors with speed and simplicity to enable shipping new solutions faster. To achieve this, ODSA strategy is centered on following three core areas:

Area 1: Enable open die to die interfaces to reduce barrier for interoperation

Area 2: Create reference designs as starting points for allowing technology development

Area 3: Define business reference workflows for enabling reusable, open practices

The 1st International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2022), endorsed by OCP/ODSA working group, is a new workshop targeting on researches with an interpenetration effect between academia and industry: on one hand, this workshop helps researchers understand the latest progress on chiplet-powered architectures for data-intensive applications and ML/HPC-motivated chiplet designs; on the other hand, it helps promote the open chiplet standards to foster collaborations on further development of the chiplet ecosystem. The major objective of this workshop is to bring researchers from academia and industry together to communicate their ideas, share knowledge of advanced technologies and new development on but not limited to the following topics:

Chiplet-based accelerator level parallelism (ALP)

Chiplet architecture for large scale system design

Physical and logical inter-die interface design for heterogeneous architectures

Coherent and non-coherent data sharing protocols via fast chiplet interconnection

Chiplet architectures for in-memory computing and other emerging technologies

ODSA-based 3D architecture for efficient ML acceleration

Chiplet-based secure computing

Power evaluation and performance modeling of chiplet architecture

Software optimization framework with fast inter-chiplet network

Chiplet topology aware ML optimizations

Organizers

Weifeng Zhang, Alibaba Cloud
Dr. Weifeng Zhang is a fellow of Alibaba Cloud Intelligence and the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure. He is also a member of the Board of Directors at MLCommons™ (MLPerf™). At Alibaba, Weifeng is in charge of heterogeneous computing technology ranging from AI accelerators and systems, benchmarking, AI compiler, performance co-optimizations, and the unified scalable heterogeneous acceleration platform for IoT, edge and datacenter. Weifeng received his PhD in Computer Science from University of California, San Diego (UCSD).

Dharmesh Jani, Meta Platforms
Dharmesh Jani (‘DJ’) is Open Ecosystem lead at Meta and has been an active member of OCP since 2012. He is also co-chair of the OCP Incubation Committee and involved in multiple OCP projects such as Open Domain Specific Accelerator (ODSA) and Sustainability. Prior to Meta, he has worked in Fortune 500 companies leading product development as well as in startups building zero to one businesses. He has BTech from IIT-Bombay, MS from UCLA and MBA from UC-Berkeley (Haas).

Michael Taylor, University of Washington
Dr. Michael Taylor is a professor at Paul Allen School of Computer Science and Engineering, University of Washington. Prior to joining UW, he was a Visiting Research Scientist at Google and a tenured professor at the University of California San Diego. Dr. Taylor received a Ph.D. in Electrical Engineering and Computer Science from MIT, and was lead architect of the 16-core MIT Raw tiled multicore processor, one of the earliest multicore processors. His scalable mesh of cores architecture was adopted by Intel Skylake SP recently, and his research on dark silicon and the utilization wall fed into the ITRS 2008 report that led Mike Mueller of ARM to coin the term “dark silicon”.

Yuan Xie, DAMO Academy, Alibaba Group
Dr. Yuan Xie is a professor at University of California, Santa Barbara and the founder of the SEAL lab. He received his Ph.D. degree from Princeton University and was with IBM Microelectronics Division's Worldwide Design Center, Pennsylvania State University, AMD Research, and UCSB. He is a Fellow of IEEE, a Fellow of ACM, and a Fellow of AAAS, and a recipient of NSF CAREER Award and IEEE Computer Society Edward J. McCluskey Technical Achievement Award in 2020.

Committees

Program Committee:

Michael Taylor, University of Washington

Rakesh Kumar, UIUC

Yuan Xie, University of California, Santa Barbara

Kevin Cao, Arizona State University

Tushar Krishna, Georgia Tech

Weifeng Zhang, OCP / Alibaba Cloud

Guoyang Chen, Alibaba Group

Rohit Mittal, Google

Dharmesh Jani, OCP / Meta (Facebook)

Ravi Aggarwal, Meta (Facebook)

Halil Cirit, Meta (Facebook)

Carole-Jean Wu, Meta and Arizona State University

Publicity Committee:

Archna Haylock, OCP

Cliff Grossner, OCP

Dirk Van Slyke, OCP

Speakers

Track	Title	Speaker(Company)	Presentation
	Opening Remarks	HipChips Program Committee: Dharmesh Jani (Meta)	Slides
Keynote	Memory Centric Computing	Prof. Onur Mutlu (ETH Zurich)	Slides
Chiplet Design & Architecure	Chiplet-based Waferscale Computing	Dr. Rakesh Kumar (UIUC)	Slides
Standards and ECO	OCP Open Domain Specific Architecture(ODSA): Approach to Creating Open Chiplet Ecosystem under OCP	OCP ODSA Leads: Bapi Vinnikota (BRCM) Dharmesh Jani (Meta)	Slides
Standards and ECO	OCP Open Domain Specific Architecture (ODSA)'s Bunch of Wire (BoW) Interface for Die to Die Applications	OCP ODSA Leads: Bapi Vinnikota (BRCM) Elad Alon(BCA) Jayaprakash B. (Cisco)	Slides
Standards and ECO	Redefining Computing Architecture Boundaries with Off-Package Chiplets - An Energy Centric Computing Perspective	Allan Cantle (Nallasway)	Slides
SW for Chiplets	HALO: a compiler framework for heterogeneous chiplet architectures with near-zero interconnect latencies	Weiming Zhao (Alibaba) Weifeng Zhang (Alibaba)	Slides
Keynote	The Case for a Universal Chiplet Revolution	Cliff Young (Google Rohit Mittal (Google)	Slides
Chiplet Design & Architecure	HPC/AI system opportunity with integrated photonics chiplets	Eduard Roytman (Intel)	Slides
Standards and ECO	What is the right Die-to-Die Interface? A Comparison Study	Shahab Ardalan Bapi Vinnikota (BRCM) Tawfik Arabi (AMD) Elad Alon (BCA)	Slides
Chiplet Design & Architecure	Heterogeneous Chiplet-based Architecture for In-Memory Acceleration of DNNs	Gokul Krishnan (ASU) Kevin Cao (ASU)	Slides
Chiplet Design & Architecure	Dual-Stripline Configuration for Efficient Signal Routing in the Bunch-of-Wires (BOW) Interface	Shalabh Gupta (IIT Bombay)	Slides Video
Chiplet IO	Design Space for Chiplet IO	Ken Chang (Cadence)	Slides
SW for Chiplets	Software-defined Design for Systems of Chiplets	Duncan Haldane (JTIX)	Slides
Keynote	Chiplet’s March to the 3D V-Cache™ and Beyond	Dr. John Wuu (AMD) Raja Swaminathan (AMD)	Slides
Chiplet Design & Architecure	Configurable IO Chiplet Architecture	Rishi Chugh (Cadence)	Slides
Chiplet Design & Architecure	Hyperscaler use cases and challnges for hetergeneous integration	Ravi Agarwal (Meta) Dharmesh Jani (Meta)	Slides
Chiplet Design & Architecure	Glass Interposer Integration of Logic and Memory Chiplets: PPA and Power/Signal Integrity Benefits	Sung-Kyu Lim (GATech) Ravi Agarwal (Meta)	Slides
Standards and ECO	Chiplets and Sustainability	Srilatha (Bobbie) Mann (Meta) Carole Jean Wu (Meta)	Slides
Keynote	Chiplets open the world of collaboration	Bob Brennan (Intel)	Slides
Chiplet Design & Architecure	Cost-Aware Exploration for Chiplet-Based Architecture with Advanced Packaging Technologies	Tianqi Tang (UCSB) Yuan Xie (UCSB)	Slides
Chiplet Design & Architecure	Designing and Pathfinding Scale-out Chiplet Based Systems	Puneet Gupta (UCLA)	Slides Video
Chiplet Design & Architecure	Using In-Chip Monitoring and Deep Data Analytics for High Bandwidth Die-to-Die Characterization	Alex Burlak (proteanTecs)	Slides
Chiplet Design & Architecure	High-Bandwidth Density, Energy-Efficient, Short-Reach Signaling that Enables Massively Scalable Parallelism	John Wilson (NVidia)	Slides
Chiplet Design & Architecure	The Road to Data Center Power Efficiency	Tawfik Arabi (AMD) Anshuman Mittal (AMD)	Slides
	Closing Remarks	HipChips Program Committee: Weifeng Zhang (Alibaba)	Slides

Venue

HiPChips Conference is colocated with  ISCA 2022
The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and research results in computer architecture. In 2022, the 49th edition of ISCA will be held in New York City, New York, USA.