The HiPChips Conference

Call for Paper

Machine learning (ML), high performance computing (HPC), and the convergence of both are becoming the major driving force to define future computer architectures in both data center and edge. To meet the computation demands from these workloads, heterogeneous computing with domain-specific accelerators (DSA) emerges as a new computing paradigm to take advantage of native hardware performance. While accelerator architecture continues evolving to integrate more units/devices to boost its computing horsepower, the increasing cost and power consumption of silicon give rise to chiplet architecture.

The modularized design in chiplet architecture brings up several benefits: 1) Reduce the complexity of traditional monolithic system-on-a-chip (SoC) design and overcome the chip area limit imposed by the reticle size of the semiconductor process. 2) Lower power consumption via mix-and-matching existing and/or new components and integrating them into a single package. 3) Shorten the development time and improve yield to lower the manufacturing costs.

However, chiplet architecture also faces a few challenges: 1) Lack of standards and tools to allow different pieces of silicon across vendors to work seamlessly through a common interface. 2) Enabling resource sharing among chiplets for composable computing. 3) Chiplet interconnect for high communication bandwidth and low latency, especially when the chip area gets close to the wafer scale. 4) Power and performance optimizations for large-scale spatial parallelism on chip.

The 3rd International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2023) aims to address these challenges and how they impact on the designs of chiplet-based architecture and software ecosystem. The major objective of this workshop is to bring the latest research and development from academia and industry together and foster closer collaboration to push the technologies forward. This workshop will focus on but not limited to the following topics:
Architecture:

Chiplet-enabled architectures with emerging technologies (e.g., in-memory computing, optical computing, quantum computing, etc)

Hardware software co-designs for chiplet architecture

High performance computing architectures enabled by fast interconnect

Power and performance modeling for chiplet architectures

Interconnect:

Interconnect technologies for coherent and non-coherent data sharing

Emerging on-chip interconnect for large-scale heterogeneous computing

Novel software optimizations and scheduling with inter-chiplet network

For any submission information, please send your requests to organizers at hipchips2023@gmail.com, due by April 30th .

Organizers

Weifeng Zhang, Lightelligence
Dr. Weifeng Zhang is the Chief Architect and VP of Software at Lightelligence Inc, responsible for hardware software co-design and software ecosystem to empower optical computing and interconnect technologies. Prior to joining Lightelligence, Weifeng was a fellow of Alibaba Cloud and the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure. He was a founding member of the Board of Directors at MLCommons™ (MLPerf™) and currently serves as the Tech Chair of AI Co-Design Workgroup at Open Computing Project Foundation (OCP). Weifeng received his PhD in Computer Science from University of California, San Diego (UCSD).

Dharmesh Jani, Meta Platforms
Dharmesh Jani (‘DJ’) leads Infrastructure Technology Ecosystem and Partnerships at Meta and has been an active member of OCP since 2012. He is also co-chair of the OCP Incubation Committee where he started the OCP strategic initiatives, launched multiple projects such Sustainability and is a founding member of the Board of Directors for UCIe consortium. Prior to Meta, he has worked in Fortune 500 companies leading product development as well as in startups building zero to one businesses. He has BTech from IIT-Bombay, MSEE from UCLA and MBA from UC-Berkeley (Haas).

Peipei Zhou, University of Pittsburgh
Peipei Zhou is an assistant professor of the Electrical Computer Engineering (ECE) department at the University of Pittsburgh. She has over 10 years of experience in hardware and software co-design. She has published 20+ papers in top-tier IEEE/ACM computer system and design automation conferences and journals including FPGA, FCCM, DAC, ICCAD, ISPASS, TCAD, TECS, TODAES, IEEE Micro, etc. She won the 2019 Donald O. Pederson Best Paper Award from the IEEE Council for Design Automation (CEDA), the 2018 IEEE ISPASS Best Paper Nominee and ICCAD Best Paper Nominee.

Speakers

	Dr. Fred Chong Professor, University of Chicago Fred is the Seymour Goodman Professor in Department of Computer Science at University of Chicago, Chief Scientist for Quantum Software at ColdQuanta, and the Lead Principal Investigator for the EPiQC Project (an NSF Expedition in Computing). Chong is a member of the National Quantum Advisory Committee (NQIAC) to the President and Secretary of Energy on the National Quantum Initiative Program. Fred received his Ph.D. from MIT in 1996, and was a faculty member and Chancellor's fellow at UC Davis (1997-2005), a Professor of Computer Science, Director of Computer Engineering, and Director of the Greenscale Center for Energy-Efficient Computing at UCSB (2005-2015). He is a fellow of the IEEE and a recipient of the NSF CAREER award, the Intel Outstanding Researcher Award, and 13 best paper awards.
	Syrus Ziai VP Engineering, Eliyan Corporation Syrus is Co-Founder of Eliyan, a leader in the chiplet industry. He has worked on near-reticle chips for the over 25 years. Prior to Eliyan Syrus led silicon and systems development of complex SoCs as VP of Engineering at Nuvia, PsiQuantum, and Qualcomm. He holds a BS EE from Rice and MS EE from Stanford, and is inventor on over 10 patents.
	Dr. Huaiyu Meng Co-Founder & CTO, Lightelligence PhD in Electrical Engineering from MIT, focusing on integrated photonics in CMOS platform for telecom, datacom, and bio-sensing applications. At Lightelligence, Huaiyu is responsible for product definition and technology roadmap planning.
	Dr. Yarui Peng Assistant Professor, University of Arkansas Prof. Peng received the B.S. degree from Tsinghua University in 2012 and Ph.D. in School of Electrical and Computer Engineering from Georgia Institute of Technology in 2016. He collaborates with the NSF Engineering Research Center for Power Optimization of Electro-Thermal Systems and the UA Power Group. His research interests are in the areas of computer-aided design, analysis, and optimization for emerging technologies and systems, such as 2.5D and 3D ICs, high band-gap power electronics and systems, and high-efficiency digital designs and memory systems. He is the recipient of best-in-session award in SRC TECHCON 14 and best student paper award in ICPT 16. He received NSF CAREER Award in 2021.
	Dr. Jayaprakash Balachandran D-Matrix Jayaprakash Balachandran (JP) leads advanced packaged and system development efforts at d-Matrix. He also leads PoC and interop workgroups at OCP-ODSA. Prior to d-Matrix, he was with Cisco Compute Server Business Unit. JP has Masters from IISc Bangalore and PhD from IMEC, Belgium.
	Dr. Navid Asadi Assitant Professor, University of Florida Dr. Asadi is an Assistant Professor in ECE Department at the University of Florida with an affiliation to the Materials Science and Engineering department. He is the Director of the Security and Assurance (SCAN) Lab and serves as the associate director of the Microelectronics Security Training (MEST) center. He has received his NSF CAREER award in 2022, several best paper awards from IEEE International Symposium on Hardware Oriented Security and Trust (HOST) and the ASME International Symposium on Flexible Automation (ISFA), and D.E. Crow Innovation award from University of Connecticut. He is the founder and general chair of the IEEE Physical Assurance and Inspection of Electronics (PAINE) Conference.
	Sunil Gupta Chiplet R&D, Meta Sunil Gupta obtained his Ph.D. in Electrical Engineering from The University of Texas at Austin. His areas of interest are Chiplets, Signal and Power integrity, Circuit Design and Silicon Validation. His work has resulted in presentations and publications at various conferences such as EMC+SIPI, ECTC, EPEPS and DesignCon.
	Dr. Kaisheng Ma Assistant Professor, Tsinghua University Principal Investigator of ARChip Lab at Tsinghua University. His research focuses on computer architecture, implanted devices, AI Algorithms Design, focusing on interpretation, robustness and compact model design.
	Siamak Tavallaei CXL Advisor to Board, CXL Consortium Siamak joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. He is currently the Incubation Committee Representative for OCP Server Project, and has served as Chief Systems Architect at Google Cloud Platforms, Senior Principal Architect at Microsoft Azure’s Hardware Architecture team, a Distinguished Technologist at HP, a Principal Member Technical Staff at Compaq.
	Durgesh Srivastava Sr. Director, Nvidia Durgesh is the Data Center Product Architect and Sr. Director at Nvidia. His work focuses on next generation Data Center SoC and Systems Innovation, including desegregated architecture, memory pooling, accelerator as a Peer, etc.
	Dr. Suresh Subramaniam Distinguished Engineer, OCP / Apex Semiconductor Suresh received his PhD from USC and MBA from Leavey School of Business, Santa Clara University. His interests are in Signal and Power Integrity, Advanced Packaging and Systems design, chip I/O sub-system architecture. Suresh previously worked at Xilinx, AMD, Applied Micro, Ericsson, and several startups. He has been actively involved in the OCP ODSA sub-project and is a member of the DesignCon Technical Program Committee.
	Nir Sever Sr. Director of Business Development, proteanTecs Nir has over 30 years of technological and managerial experience in advanced VLSI engineering, including the COO position at Tehuti Networks for 10 years and Senior Director of VLSI Design and Technologies at Zoran Corporation. Prior to that, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions, and Zoran Microelectronics. Nir holds a B.Sc in Electrical Engineering from Israel Institute of Technology, Technion.
	Dr. Debendra Das Sharma UCIe Chair, Sr Fellow, Intel Chief Architect of I/O Technologies and Standards: Responsible for driving Intel-wide critical interconnect technologies in PCIe, CXL, Intel’s coherency interconnect, on-package interconnects, as well as on-die standards (PIPE, LPIF, CPI, SFI).
	Dr. Bapi Vinnakota ODSA Project Lead, OCP Bapi currently leads the Open Domain-Specific Architecture sub-project, within the Open Compute Project. The ODSA has active volunteers from over 50 companies and has 8 active workstreams that aim to define an open Chiplet marketplace, and several key Chiplet-related activities in flight that are essential for establishing an open Chiplet economy. Bapi received his PhD in computer engineering from Princeton Univeristy.

Schedule

The Marriott World Center Orlando
Orlando, Florida, USA
June 17th, 2023, 9:00am - 5:30pm ET
Zoom Call: 831 3030 9538

Session	Speaker	Title	Materials
Open Remark 9:00-9:05am	Prof. Peipei Zhou Co-Chair
Keynote 9:05-9:50am	Dr. Fred Chong Univ Chicago	Modular, Distributed, and Hybrid Systems with Quantum Chiplet	slides video
Invited talk 9:50-10:15am	Syrus Ziai Eliyan	High Performance Die-to-Die PHYs for Chiplets	slides video
Invited talk 10:15-10:40am	Dr. Huaiyu Meng Lightelligence	Enable large scale computing with 3D optical chiplet interconnect	slides video
Coffee Break 10:40-10:50am
Keynote 10:50-11:35am	Dr. Yarui Peng Univ Arkansas	Chiplet-Package Co-Design CAD Tools for Heterogeneous-System-in-Package (HeSiP)	slides video
Invited talk 11:35-12:00pm	Jayaprakash B. D-Matrix	Large Scale Generative Inference Acceleration with Chiplets and In-Memory Compute	slides video
Invited talk 12:00-12:25pm	Sunil Gupta Meta	Chiplet Usecases in Consumer Electronics: Opportunities and Challenges	slides video
Mid Remark 12:25-12:30pm	DJ Co-Chair
Lunch Break 12:30-2:00pm
Keynote 2:00-2:45pm	Dr. Navid Asadi Univ Florida	Physical Assurance of Microelectronics from Chiplets to Systems	slides
Invited talk 2:45-3:10pm	Prof. Kaisheng Ma Tsinghua University	Introducing ACC 1.0: Advanced Cost-driven Chiplet Interface Standard	slides video
Invited Talk 3:10-3:35pm	Nir Sever proteanTecs	Mornitoring High Density D2D Interconnect	slides video
Coffee Break 3:35-3:45pm
Invited talk 3:45-4:10pm	Dr. Subramaniam OCP/Apex	A chiplet based SmartNIC platform using an open die to die standard (BoW)	slides
Invited talk 4:10-4:35pm	Siamak Tavallaei CXL Consortium	CXL-enabled systems start their roots on a die!	slides
Invited talk 4:35-5:00pm	Durgesh Srivastava Nvidia	Chiplet Security Threat Analysis	slides
Invited talk 5:00-5:25pm	Dr. Debendra Sharma UCIe Consortium	Universal Chiplet Interconnect Express (UCIe)TM: An open standard approach for constructing future SoCs	slides
Invited talk 5:25-5:50pm	Bapi Vannikota OCP	New and Open Chiplet Ecconomy
Close Remark 5:50-5:55pm	Dr. Weifeng Zhang Co-Chair	Chiplets for composable polymorphic AI architectures	slides

Venue

HiPChips Conference is colocated with  ISCA 2023
The ACM 50th Annual International Symposium on Computer Architecture (ISCA-50)
Orlando, Florida, USA