The HiPChips Conference

Call for Paper

Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever increasing computing demands in today’s data centers. Heterogeneous computing with domain-specific architectures (DSAs) brings many opportunities to boost compute horsepower via scaling up and scaling out the computing system. While accelerator architecture continues evolving to integrate more compute elements into a single chip, chiplet-based heterogeneous architecture is favored to keep scaling up and scaling out the system as well as to reduce the design complexity and cost stemming from the traditional monolithic chip design.

However, how to interconnect computing resources and orchestrate heterogeneous chiplets is the key to success. With the diversity and evolving demands of different AI workloads, chiplet architecture faces a few challenges: 1) Lack of mature unified standards and tools to allow different pieces of silicon across vendors to integrate seamlessly through a common interface. 2) Composable architecture design to enable resource sharing and data coherency. 3) Extended reach of chiplet interconnect with high bandwidth and low latency, especially when the chip area gets close to the wafer scale. 4) Software programming model for heterogeneous parallelism on chip with optimal power and performance.

The 4th International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2024) aims to address these challenges and how they impact on the designs of chiplet-based architecture and software ecosystem. The major objective of this workshop is to bring together the latest research and development from academia and industry and foster closer collaboration to push the technologies forward. This workshop will focus on but not limited to the following topics:
Architecture:

Heterogeneous chiplet architectures with emerging technologies (e.g., in-memory computing, optical computing, quantum computing, etc.)

Composable microarchitectures enabled by fast chiplet interconnect

Advancement of in-package communication, routing algorithm in SiP, and other related packaging technologies (testing, thermal, etc.)

Security of chiplet system

Software and Ecosystem:

Hardware software co-designs on chiplet architecture

Programming model, scheduling and optimizations of chiplet systems

Power, thermal, and sustainability studies for heterogeneous chiplet systems

Design space exploration (DSE) in chiplet systems

Organizers

Weifeng Zhang, Lenovo Research
Dr. Weifeng Zhang is a Corporate VP of Lenovo Group and Director of Intelligent Computing & Wireless Research Labs at Lenovo Research. Prior to joining Lenovo, Weifeng was the Chief Architect and VP of Software at Lightelligence Inc, a fellow of Alibaba Group and the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure. He was a founding member of the Board of Directors at MLCommons™ (MLPerf™) and currently serves as the Chair of the AI Co-Design Workgroup at the Open Compute Project Foundation (OCP) and the Program Committee for the OCP Future Technology Symposiums on AI/HPC technologies. Weifeng received his PhD in Computer Science from the University of California, San Diego (UCSD).

Peipei Zhou, Brown University
Dr. Peipei Zhou is a Tenure-Track Assistant Professor at Brown University, School of Engineering. She led the ARC (Customized Computer Architecture Research Center https://github.com/arc-research-lab) Group. She obtained a Ph.D. in Computer Science from the University of California, Los Angeles in 2019 supervised by Prof. Jason Cong, who leads UCLA VAST(VLSI Architecture, Synthesis and Technology) Group. Peipei's research interest is in Customized Architecture and Programming Abstraction for Applications including Healthcare, e.g., Precision Medicine and Artificial Intelligence. She received the 2019 TCAD Donald O. Pederson Best Paper Award in recognition of the best paper published in the IEEE Transactions on CAD in the two calendar years preceding the award and the 2023 IGSC Best Viewpoint Paper Nominee, 2018 ICCAD Best Paper Nominee, and 2018 ISPASS Best Paper Nominee.

Dharmesh Jani, Meta Platforms
Dharmesh Jani (‘DJ’) is a seasoned technology leader with over 25 years of experience in engineering, product management, and business strategy. DJ serves as Director of Open Ecosystems at Meta, focusing on development of open technologies for AI infra. He co-chairs the Open Compute Project (OCP) Incubation Committee and has played a key role over the years in launching Open Chiplets, Sustainability and Open Systems for AI initiatives in OCP. Before joining Meta, DJ founded the CloudLabs team at Flex, was at Rockwell Science Center, designing ultra-high-speed circuits that were integrated into the Mars Orbiter Laser Altimeter (MOLA) system. He then transitioned to system design, developing the world's first terrestrial FEC-based long-haul optical transmission system. At Infinera, he was involved in developing communication system based on the industry's first photonic integrated circuit. He also held roles at companies like Intel, Semtech, and two startups all in 100G semiconductor product line management. DJ holds a B.Tech from IIT-Bombay, an MSEE from UCLA, and an MBA from UC Berkeley's Haas School of Business.

Chester Park, Konkuk University
Dr. Chester Park is a Professor in the Department of Electrical and Electronics Engineering, Konkuk University, South Korea, where he is currently working on algorithm and architecture co-optimizations using virtual platform based SoC simulations. Before joining academia, he was with Samsung Electronics, Giheung, South Korea, and Ericsson Research, CA. He received the Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2006.

Prudhvi Nethi, Nvidia
Prudhvi Nethi is an Engineering Manager at NVIDIA, where he leads the development of manufacturing test and diagnostic solutions for data center products. Previously, he led the product development of data center computing products from prototype to production at Meta. Before that, he focused on product development and diagnostics for the Intel Chipset product line at Intel. Prudhvi holds a Master’s degree in Electrical Engineering from Portland State University.

Speakers

	Dr. Arindam Mallik , Department Director, IMEC Arindam Mallik leads Compute System Architecture (CSA) department at imec. He is a technologist enabling HW-SW co-design at the cross-point of AI algorithms, computer architecture, and novel technology solutions. Arindam has spent the past 20 years pushing the boundaries of technology research to provide novel solutions with a direct impact on the semiconductor industry. He has authored or co-authored more than 100 papers in international journals, conference proceedings, and holds number of relevant patents. He received M.S. and PhD degree in Electrical Engineering and Computer Science from Northwestern University, USA in 2004 and 2008, respectively.
	Dr. Tushar Krishna , Associate Professor, Georgia Institute of Technology Tushar is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology. He has also been a visiting professor at MIT, Harvard University and a researcher at Intel. He received a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E from Princeton University (2009), and a B.Tech from the Indian Institute of Technology (IIT) Delhi (2007). His research spans computer architecture, interconnection networks, networks-on-chip (NoC), and AI/ML accelerator systems. He was inducted into the HPCA Hall of Fame (2022) and honored by the “Class of 1940 Course Survey Teaching Effectiveness Award” (2018), the “Roger P. Webb Outstanding Junior Faculty Award” (2021), the “Richard M. Bass/Eta Kappa Nu Outstanding Junior Teacher Award” (2023), and the “Roger P. Webb Outstanding Mid-career Faculty Award” (2024).
	Dr. Debendra Das Sharma UCIe Chair, Sr Fellow, Intel Chief Architect of I/O Technologies and Standards: Responsible for driving Intel-wide critical interconnect technologies in PCIe, CXL, Intel’s coherency interconnect, on-package interconnects, as well as on-die standards (PIPE, LPIF, CPI, SFI).
	Dr. David Pan, Chair Professor, UT Austin David Z. Pan (Fellow of ACM, IEEE, and SPIE) directs the UT Design Automation (UTDA) Lab. His research interests include electronic design automation, machine learning, design for manufacturing, and emerging technologies. He has published 500+ refereed papers and graduated 52+ PhDs/postdocs who are holding key academic/industry positions. He has won the SRC Technical Excellence Award in 2013 and 21 Best Paper Awards in premier EDA and chip venues, among others. David obtained his PhD in Computer Science from UCLA.
	Dr. Kaisheng Ma, Associate Professor, Tsinghua University Kaisheng is an Associate Professor in Institute for Interdisciplinary Information Sciences (IIIS), Tsinghua University. He received his Ph.D. in Computer Science and Engineering at the Pennsylvania State University. His research focuses on Robust and Efficient AI Algorithms, Post-Moore Architecture, and High-Performance Chips. Dr. Ma has published more than 50 papers on top conferences including NeurIPS, ICCV, AAAI, CVPR, ISCA, ASPLOS, MICRO, HPCA, DAC etc. He has won many awards and honors, including 2024 HPCA Distinguished Artifact Award (1/410), 2022 CCF Integrated Circuit Early Career Award, 2020 Springer Nature Research Highlights from China Collection Award, 2017 ASP-DAC Best Paper Award, 2016 IEEE MICRO Top Picks, 2015 HPCA Best Paper Award, etc.
	Durgesh Srivastava, CTO, MIPS Durgesh is the CTO at MIPS. Before MIPS, he held the Senior Director / Data Center Product Architect at Nvidia and various tech/management positions at Intel. Durgesh is an alumnus of IIT Kanpur and Hong Kong University of Science and Technology.
	Dr. Bapi Vinnakota, Program Manager, NIST Bapi Vinnakota is a program manager with the NAPMP in CHIPS R&D Office in NIST. Prior to joining NIST, he started and led the Open Domain-Specific Architecture sub-project, within the Open Compute Project to create and establish chiplet economy. He also participated in the Manufacturing Roadmap for Heterogeneous Integration and Electronic Packaging, a roadmap effort sponsored by NIST and led by Prof. Subu Iyer at UCLA and SEMI. Bapi received his Ph.D. from Princeton University.
	Dr. Jiaqi Gu, Assistant Professor, Arizona State University Jiaqi is an Assistant Professor of the School of Electrical, Computer and Energy Engineering at Arizona State University. He received his B.E. degree from Fudan University in 2018, and the Ph.D. degree in Electrical and Computer Engineering from The University of Texas at Austin in 2023. His research interests include emerging technology for next-generation AI computing systems, hardware-algorithm co-design, AI/ML for hardware design, and electronic-photonic design automation.
	Dr. Fitzgerald Sungkyung Park, Professor, Pusan National University Fitzgerald Sungkyung Park took his Ph.D. degree in electronics engineering from Seoul National University, Korea. He worked for Samsung Electronics, Electronics and Telecommunications Research Institute (ETRI), and Ericsson, Inc., USA, where he developed circuits for various transceivers. After joining Pusan National University, his research interests include design and modeling of SoC, hardware accelerators, and virtual platforms for neural networks and 6G.
	Dr. Srikant Bharadwaj, Sr. Researcher, Microsoft Srikant Bharadwaj is a Senior Researcher at Microsoft working on hardware-software co-design for machine learning and high-performance computing applications in the Systems Innovation Group. Srikant received his Master’s and PhD degree in Electrical and Computer Engineering from Georgia Institute of Technology. Before joining Microsoft, Srikant worked as a Senior Researcher at AMD Research for about 4.5 years.
	Venkat Ramesh, Production System Lead, Meta Venkat Ramesh is a Production Systems Engineer working in Meta's Infrastructure Org. Venkat leads various initiatives on diagnostics development, telemetry gathering and performance for AI silicon, systems and training clusters. In his past life, he worked on telemetry software, as well as performance engineering teams at a couple of Flash vendors.
	Lihong Cao, Sr. Director, ASE Group Lihong Cao is a senior director of engineering/technical marketing at ASE US Inc. She has comprehensive experience driving new product and advanced packaging technology development, new product introduction, quality and reliability, Fab/OSATs processes and root cause analysis. Responsible for advanced packaging architecture, chiplets interconnect, advanced packaging technology development (2.5D/3D, FOCoS, Embedded Bridge, SIP, SiPh) for Chiplets and Heterogeneous Integration, Technology promotion, Strategic planning and Business engagement. She leads chiplets Die to Die interconnect standardization effort in UCIe (Universal Chiplets Interconnect Express) consortium as Board of Director of ASE.
	Dr. Saeed Fathololoumi, System Lead, Intel Saeed Fathololoumi is a Principal Engineer and Photonic Architect at Intel, developing co-packaged optics and optical compute interconnect for AI/ML ASIC connectivity applications. He has led development of many industry firsts, including OCI chiplets for connecting XPUs and fully operation co-package optic connectivity with switch ASIC. He worked at Elenion Technologies, Mellanox, Kotura and National Research Council of Canada, previously. He obtained his PhD in Electrical and Computer Engineering from University of Waterloo.
	Nathan Kalyanasundharam, Corporate Fellow, AMD Nathan is the lead architect of AMD’s Infinity Fabric, responsible for delivering coherent interconnect protocol and technology across all AMD products. He is passionate about open standards to enable heterogenous computing. He is a member of the Board of Directors at Compute Express Link (CXL) and Universal Chiplet Interconnect Express(UCIE) consortia.
	Dr. Koichi Yamaguchi, Meta Koichi Yamaguchi received his B.E. and M.E. degrees in Electrical Engineering from the Tokyo Institute of Technology, and Ph.D. in Engineering from Tokyo University. He was a visiting scholar at Stanford University, and worked at NEC, Renesas Electronics, MegaChips Technology America, and Intel (mixed-signal modeling/verification and system design of high-speed serial transceivers). He served as a member of the wireline subcommittee for ISSCC from 2009 to 2014. Now he works at Meta on signal and power integrity, high-speed I/O interface for next-generation AR/VR devices.
	Dr. Mahmut Yilmaz, Director, Nvidia Mahmut Yilmaz earned his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Duke University in 2006 and 2009, respectively. Currently, he serves as a Director of Engineering at NVIDIA, where he specializes in enhancing chip reliability and quality, silicon lifecycle management, and developing the NVIDIA MATHS and In-System Test architecture.

Schedule

The AT&T Hotel and Conference Center, Room #103
Austin, Texas, USA
November 2^nd, 2024, 8:15am - 5:00pm CT
Zoom Call: Join the meeting (Meeting ID: 851 9318 4152, Passcode: 765776)

Session	Speaker	Title	Materials
Open Remark 8:15-8:30am	Chester P. & Peipei Z. Co-Chairs
Keynote 8:30-9:00am	Arindam Mallik IMEC	The Evolution and Impact of Digital Computing Demand on the Semiconductor Industry
Invited Talk 9:00-9:20am	Fitzgerald Park Pusan National Univ	Pre-RTL Simulation Based Design Space Exploration for Multi-chiplet Dataflows
Invited talk 9:20-9:40am	Kaisheng Ma Tsinghua Univ	Interconnection Network Architecture based on Advanced Packaing: From Chiplets to Systems
Invited talk 9:40-10:00am	Bapi Vinnakota NIST	CHIPS NAPMP: Leveraging Advanced Packaging for Chiplets
Coffee Break 10:00-10:30am
Keynote 10:30-11:00am	David Pan UT Austin	AI for 3D Heterogeneous Integration of Everything: Digital, Analog, RF, Photonics, and beyond
Invited talk 11:00-11:20am	Dharmesh Jani Meta	Silicon Dreams: Towards the AI Singularity
Invited talk 11:20-11:40am	Durgesh Srivastava MIPS	Overcoming Manufacturing and Packaging Challenges for Chiplet Integration: A Small Company's Perspective
Invited talk 11:40-12:00pm	Saeed Fathololoumi Intel	Connecting XPUs using Optical Compute Interconnect Chiplets
Lunch Break 12:00-1:00pm
Keynote 1:00-1:30pm	Nathan K. AMD	Ultra Accelerator Link (UALink)
Invited talk 1:30-1:50pm	Debendra Sharma UCIe Consortium	UCIeTM 2.0: Progress towards open chiplet ecosystem
Invited talk 1:50-2:10pm	Jiaqi Gu ASU	Cross-Layer Co-Design and Design Automation Toward Reconfigurable, Robust, and Secure Heterogeneous Electronic-Photonic AI Eco-systems
Invited talk 2:10-2:30pm	Tushar Krishna Georgia Tech	TACOS: Topology-Aware Collective Algorithm Synthesizer for Diverse AI Platforms
Invited talk 2:30-2:50pm	Venkat Ramesh Meta	Hardware Diagnostics: Spanning Hardware Lifecycle for Silicon through Clusters
Coffee Break 2:50-3:20pm
Keynote 3:20-3:50pm	Lihong Cao ASE	Advanced Packaging Technology for Chiplet and Heterogeneous Integration
Invited talk 3:50-4:10pm	Srikant Bharadwaj Microsoft	InC2: Design of Interconnection Systems for Composable Chiplet Architectures
Invited talk 4:10-4:30pm	Koichi Yamaguchi Meta	3D Chiplet Technologies for AR Applications
Invited talk 4:30-4:50pm	Mahmut Yilmaz Nvidia	Using NVIDIA MATHS for Silicon Lifecycle Management: From Wafer Probe to In-System Test and RMA
Close Remark 4:50-5:00pm	Weifeng Zhang Co-Chair	Polymorphic Architecture: from chiplets to large-scale computing culsters

Venue

HiPChips Conference is colocated with  MICRO 2024
The 57^th IEEE/ACM International Symposium on Microarchitecture®
The AT&T Hotel and Conference Center, Room #103
Austin Texas, USA