The HiPChips Conference

Call for Paper

Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever increasing computing demands in today’s data centers. Heterogeneous computing with domain-specific architectures (DSAs) brings many opportunities to boost compute horsepower via scaling up and scaling out the computing system. While accelerator architecture continues evolving to integrate more compute elements into a single chip, chiplet-based heterogeneous architecture is favored to keep scaling up and scaling out the system as well as to reduce the design complexity and cost stemming from the traditional monolithic chip design.

However, how to interconnect computing resources and orchestrate heterogeneous chiplets is the key to success. With the diversity and evolving demands of different AI workloads, chiplet architecture faces a few challenges: 1) Lack of mature unified standards and tools to allow different pieces of silicon across vendors to integrate seamlessly through a common interface. 2) Composable architecture design to enable resource sharing and data coherency. 3) Extended reach of chiplet interconnect with high bandwidth and low latency, especially when the chip area gets close to the wafer scale. 4) Software programming model for heterogeneous parallelism on chip with optimal power and performance.

The 4th International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2024) aims to address these challenges and how they impact on the designs of chiplet-based architecture and software ecosystem. The major objective of this workshop is to bring together the latest research and development from academia and industry and foster closer collaboration to push the technologies forward. This workshop will focus on but not limited to the following topics:
Architecture:

Heterogeneous chiplet architectures with emerging technologies (e.g., in-memory computing, optical computing, quantum computing, etc.)

Composable microarchitectures enabled by fast chiplet interconnect

Advancement of in-package communication, routing algorithm in SiP, and other related packaging technologies (testing, thermal, etc.)

Security of chiplet system

Software and Ecosystem:

Hardware software co-designs on chiplet architecture

Programming model, scheduling and optimizations of chiplet systems

Power, thermal, and sustainability studies for heterogeneous chiplet systems

Design space exploration (DSE) in chiplet systems

Organizers

Weifeng Zhang, Lenovo Research
Dr. Weifeng Zhang is a Corporate VP of Lenovo Group and Head of Intelligent Computing & Wireless Research Labs at Lenovo Research. Prior to joining Lenovo, Weifeng was the Chief Architect and VP of Software at Lightelligence Inc, a fellow of Alibaba Group and the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure. He was a founding member of the Board of Directors at MLCommons™ (MLPerf™) and currently serves as the Chair of the AI Co-Design Workgroup at the Open Compute Project Foundation (OCP) and the Program Committee for the OCP Future Technology Symposiums. Weifeng received his PhD in Computer Science from the University of California, San Diego (UCSD).

Peipei Zhou, University of Pittsburgh
Dr. Peipei Zhou is a tenure-track assistant professor in the Department of Electrical Computer Engineering (ECE) at the University of Pittsburgh. She received her PhD in Computer Science (2019) and M.S. in Electrical and Computer Engineering (2014) from UCLA, and her B.S. in Electrical and Computer Engineering (2012) from Southeast University. Her research investigates architecture, programming abstraction, and design automation tools for reconfigurable computing and heterogeneous computing. She has published 30 papers in top-tier IEEE/ACM computer system and design automation conferences and journals including FPGA, FCCM, DAC, ICCAD, ISPASS, TCAD, TECS, TODAES, IEEE Micro, etc. Her work has won the 2019 IEEE TCAD Donald O. Pederson Best Paper Award. Other awards include the 2023 ACM/IEEE IGSC Best Viewpoint Paper Finalist, the 2018 IEEE ISPASS Best Paper Nominee, and the 2018 IEEE/ACM ICCAD Best Paper Nominee.

Dharmesh Jani, Meta Platforms
Dharmesh Jani (‘DJ’) leads the AI Infrastructure Technology Ecosystem and Partnerships at Meta and has been an active member of OCP since 2012. He is also co-chair of the OCP Incubation Committee where he started the OCP strategic initiatives, launched multiple projects such as Sustainability, and is a founding member of the Board of Directors for UCIe consortium. Prior to Meta, he worked in Fortune 500 companies leading product development as well as in startups building zero to one businesses. He has a BTech from IIT-Bombay, an MSEE from UCLA, and an MBA from UC-Berkeley (Haas).

Chester Park, Konkuk University
Dr. Chester Park is a Professor in the Department of Electrical and Electronics Engineering, Konkuk University, South Korea, where he is currently working on algorithm and architecture co-optimizations using virtual platform based SoC simulations. Before joining academia, he was with Samsung Electronics, Giheung, South Korea, and Ericsson Research, CA. He received the Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 2006.

Prudhvi Nethi, Nvidia
Prudhvi Nethi is an Engineering Manager at NVIDIA, where he leads the development of manufacturing test and diagnostic solutions for data center products. Previously, he led the product development of data center computing products from prototype to production at Meta. Before that, he focused on product development and diagnostics for the Intel Chipset product line at Intel. Prudhvi holds a Master’s degree in Electrical Engineering from Portland State University.

Speakers

Schedule

The AT&T Hotel and Conference Center
Austin, Texas, USA
November 2^nd, 2024, 9:00am - 5:00pm CT

Venue

HiPChips Conference is colocated with  MICRO 2024
The 57^th IEEE/ACM International Symposium on Microarchitecture®
Austin Texas, USA