The HiPChips Conference

Call for Paper

Fast-evolving artificial intelligence (AI) algorithms such as large language models (LLMs) have been driving ever increasing computing demands in data centers as well as on the edge. While the traditional accelerator architecture continues evolving to provide more processing power within a single chip, the chiplet-based heterogeneous architecture is becoming a mainstream of chip designs due to these advantages: 1) Significant reduction of design complexity and cost due to mixed technologies and shifting away from monolithic chip design; 2) Heterogeneous chiplets can be integrated to accommodate the diversified runtime behaviors of AI applications at the chip level, boosting performance as well as increasing compute efficiency; 3) Ease of scaling up and scaling out chiplets brings new opportunities to boost compute power at the system level; 4) Leveraging on the latest technologies, such as integration of optical interconnects via interposer waveguides and laser integration.

However, how to architect, interconnect and package chiplets and orchestrate heterogeneous computing resources is the key to success. The current chiplet ecosystem faces a few challenges: 1) Lack of mature unified standards and tools to allow different pieces of silicon across vendors to integrate seamlessly through a common interface. 2) How to enable composable architecture design for better resource sharing and data coherency. 3) Extended reach of chiplet interconnect with high bandwidth and low latency, especially when the chip area gets close to the wafer scale. 4) Software programming model for heterogeneous parallelism on chip with optimal power and performance.

The 5th International workshop on the High Performance Chiplet and Interconnect Architectures (HiPChips-2025) aims to bring together the latest research and development from academia and industry communities and foster closer collaboration to address the challenges above. This workshop will focus on several key technology areas in chiplet-based architecture design and software ecosystem development. Topics will include but not limited to the followings:

Architecture:

Emerging computing technologies (such as neuromorphic / in-memory computing, optical and quantum computing) and integration with heterogeneous chiplet architecture

Optical chiplet integration approaches to enable composable microarchitectures

AI powered chiplet designs and system optimizations

Best practice of chiplet manufacturing and advanced packaging

Software and Ecosystem:

Hardware software co-designs on chiplet architecture, programming model and optimizations of heterogeneous chiplet systems

AI workload characterization and scheduling on heterogeneous chiplet systems

Performance/power optimizations for resource constrained scenarios (edge)

Chiplet-to-chiplet proprietary/standardized interface such as UCIe, NVLink etc.

Organizers

Chester Park, Konkuk University
Dr. Chester Park is a Professor in the Department of Electrical and Electronics Engineering, Konkuk University, South Korea, where he is currently working on algorithm and architecture co-optimizations using virtual platform based system simulations. In particular, he has been developing a new system simulator, NetTLMSim, that facilitates the system-level optimizations of heterogeneous chiplet system dataflow. Before joining academia, he was with Samsung Electronics, Giheung, South Korea, and Ericsson Research, CA. He received the Ph.D. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon.

Weifeng Zhang, Lenovo Research
Dr. Weifeng Zhang is Corporate VP of Lenovo Group and the Director of Intelligent Computing Lab at Lenovo Research. He currently serves as the Chair of the AI Co-Design Workgroup at the Open Compute Project Foundation (OCP) and the Program Committee for the OCP Future Technology Symposiums (AI/HPC track). Prior to joining Lenovo, Weifeng was the Chief Architect and VP of Software at Lightelligence Inc for system architecture, hardware software co-design, and software ecosystem to empower optical computing and optical interconnect technologies. Before Lightelligence, Weifeng was a fellow of Alibaba Group and the Chief Scientist of Heterogeneous Computing at Alibaba Cloud Infrastructure. He was also a founding member of the Board of Directors at MLCommons (MLPerf™). Weifeng received his PhD in Computer Science from the University of California, San Diego (UCSD).

Dharmesh Jani, Meta Platforms
Dharmesh Jani (‘DJ’) is Director at Meta leading the Infrastructure Technology Ecosystem and Partnerships and has been an active member of OCP since 2012. He is also co-chair of the OCP Incubation Committee where he started the OCP strategic initiatives, launched multiple projects such as Sustainability, Open Systems for AI and is a founding member of the Board of Directors for UCIe consortium as well as UALink. Prior to Meta, he worked in Fortune 500 companies leading product development as well as in startups building zero to one businesses. He has a BTech from IIT-Bombay, an MSEE from UCLA, and an MBA from UC-Berkeley (Haas).

Speakers

Schedule

Hotel
Seoul, Korea
October 19^th, 2025, 8:00am - 5:00pm

Session	Speaker	Title	Materials

Venue

HiPChips Conference is colocated with  MICRO 2025
The 58^th IEEE/ACM International Symposium on Microarchitecture®

Seoul, South Korea